1. Field of the Invention
The present invention generally relates to a semiconductor dynamic RAM (Random Access Memory) and, more specifically, to an arrangement of memory cells and sense amplifiers in a dynamic RAM for relaxing pitch condition imposed on the sense amplifiers and a method of operating the same.
2. Description of the Background Art
FIG. 5 schematically shows a conventional memory cell array structure of a semiconductor dynamic RAM. In FIG. 5, two bit line pairs BL1, BL1 and BL2, BL2 are shown as representatives for the purpose of simplicity.
Equalizing transistors 11 and 12 are provided on the bit line pair BL1, BL1 for equalizing potentials of the bit lines BL1 and BL1 to V.sub.cc /2 (where V.sub.cc is an operational supply potential). Both equalizing transistors 11 and 12 turn on in response to an equalizing signal EQ applied through a signal line 6 and transmit a potential V.sub.BL applied through a signal line 5 to the bit lines BL1 and BL1.
Similarly, equalizing transistors 13 and 14 are provided on the bit line pair BL2, BL2 which turn on in response to the equalizing signal EQ for equalizing the potentials on the bit lines BL2 and BL2 and for transmitting the constant potential V.sub.BL to each of the bit lines BL2 and BL2.
A sense amplifier 1 for differentially amplifying signal potentials on the bit line pair BL1, BL1 are provided on the bit line pair BL1, BL1, while a sense amplifier 2 for differentially amplifying signal potentials on the bit line pair BL2, BL2 is provided on the bit line pair BL2, BL2. A pitch P of the sense amplifiers 1 and 2 is selected to be in correspondence with that for the two bit line pairs. Consequently, the sense amplifiers 1 and 2 are a:.ranged in parallel to each other along a direction of extension of the bit lines, the bit lines BL2 and BL2 being connected to the sense amplifier 2 by means of multilayer interconnections 3 and 4 passing over the sense amplifier 1, respectively. Each of the bit line pairs BL1, BL1 and BL2, BL2 constitute so called folded bit lines, and therefore memory cells are disposed at intersections of ore bit line and every other word line in each bit line pair. More specifically, a memory cell comprising a transistor 21 and a capacitor 31 for storing information in the form of charges is disposed at an intersection of the word line WL0 and the bit line BL1. A memory cell comprising a transfer gate transistor 23 and a capacitor 33 is disposed at an intersection of the bit line BL2 and the word line WL0. A memory cell comprising a transfer gate transistor 22 and a capacitor 32 and a memory cell comprising a transfer gate transistor 24 and a capacitor 34 are respectively provided to the intersections of the word line WL1 and the bit lines BL1 and BL2.
FIG. 6 is a diagram of waveforms illustrating the operation of the dynamic RAM shown in FIG. 5, in which waveforms of signals when the word line WL0 is selected are shown. The operation of the conventional dynamic RAM will be described in the following with reference to FIGS. 5 and 6.
While an equalizing signal EQ applied to the signal line 6 is at a high level, all equalizing transistors 11 to 14 are in the on state. Therefore, the bit line potentials, that is, the ground potential GND and the supply potential V.sub.cc which appeared on each of the bit line pairs in the last memory cycle are equalized and a constant potential V.sub.BL applied through the signal line 5 is transmitted to each of the bit lines BL1, BL1, BL2 and BL2 through respective equalizing transistors 11 to 14, whereby the potential of each bit line is held at V.sub.cc /2.
After the equalizing signal EQ falls to a low level, the word line WL0 is selected by decoder means, not shown, so that the potential on the word line WL0 becomes a high level. Consequently, the transfer gate transistors 21 and 23 connected to the word line WL0 are turned on, and the information held in the memory capacitor 31 is read to the bit line BL1 while the information stored in the memory capacitor 33 is read to the bit line BL2. FIG. 6 shows a case in which the information "0" is read to the bit lines BL1 and BL2, as an example. Thereafter, the sense amplifiers 1 and 2 are brought to an active state, and the bit lines BL1 and BL2 of a lower potential are discharged to the ground potential GND, while the bit lines BL1 and BL2 of the higher level potential are charged to the supply potential V.sub.cc. In other words, the read-out signal potentials in each bit line pair are amplified. Thereafter, a pair of bit lines is selected in response to an output from a column decoder, not shown, and the signal potentials on the selected bit line pair are transmitted to data input/output lines to be externally outputted. By the time when the signal potential on the selected word line WL0 becomes low level, the information of the ground potential of GND level, that is, a low level, has been written again in the memory capacitors 31 and 33 connected to the selected word line WL0. Thereafter, the equalizing signal EQ becomes a high level, and the ground potential GND and the supply potential V.sub.cc which are the potentials on each of the bit line pairs are equalized by the equalizing transistors 11 to 14 to be V.sub.cc /2.
The data reading and the refreshing operation in the dynamic RAM are carried out by repeating the above described operation for a required number of times.
As the capacity of a dynamic RAM has been increased, each memory has been made minute. Accordingly, various device components formed in the semiconductor processes have been increasingly miniaturized. In the miniaturization, the pitch between the bit lines and the pitch between the bit line pairs can be made smaller simply in accordance with the reduction of the memory size. However, as for the sense amplifiers, the sense amp pitch P can not be made smaller in accordance with the miniaturization of the pitch between bit lines, since a large number of transistors are included in the sense amplifier and the structure thereof is complicated. Therefore, a structure such as shown in FIG. 5 has been inevitably employed in which two rows of sense amplifiers are arranged in parallel to each other and the sense amplifier 2 is arranged outside of the sense amplifier 1 by utilizing multilayer interconnections to relax the sense amp pitch P. In that case, however, sense amplifiers are arranged on two lines in parallel to each other so that the chip area is increased along with the increase of the area required for laying out the sense amplifiers, causing the increase of the cost of the dynamic RAM.
A structure such as shown in FIG. 7 has been known as one structure of the memory cell array of a conventional dynamic RAM, in which the bit line pairs are divided, a sense amplifier SA is provided at the central portion of the bit lines, only the divided bit line pair BL1, BL1 (or BL2, BL2) is connected to the sense amplifier SA to amplify the read-out potential thereon, and the read-out signal potentials are transferred to the data input/output bus in response to an output of a column decoder CD (disclosed in, for example, Japanese Patent Publication Gazette No. 46918/1986). However, in the so called shared sense amplifier structure shown in FIG. 7, the reading and the writing of data are carried out through a data input/output buffer from the side of the column decoder. Therefore, after the sensing operation, the read-out (amplified) signal potentials have to be transmitted on the data input/output bus through the divided bit lines BL2 and BL2. This means that the precharge potentials on the divided bit line pairs BL2 and BL2 are discharged, causing unnecessary power consumption. In addition, when the pitch between bit lines is made smaller, the pitch of the column decoder (unit column: decoder) as well as the pitch of the sense amplifier SA can not cope with the reduction of the pitch between bit lines in the shared sense amplifier structure, and therefore, the pitch condition of the column decoder also becomes severe.
Another structure is proposed in Japanese Patent Laying Open Gazette No. 58689/1984 in which sense amplifiers are provided on both sides of a plurality of bit line pairs, the sensing operation is carried out on the selected bit line pair by the sense amplifier on one side and the refreshing operation is carried on the non-selected bit line pair by the sense amplifier on the other side, so as to relax the pitch condition of the sense amplifiers. In this structure, however, the sense amplifiers are provided on both sides of the bit line pairs, thereby increasing the area required for the sense amplifiers as well as the area of the chip. In addition, in any of the above described structures of the prior art, one memory cell is selected in each bit line pair when one word line is selected, so that if the pitch between bit lines is made smaller, the influence of noise from adjacent bit line pairs in data reading becomes larger, making it difficult to accurately amplify the read-out signal potentials by the sense amplifiers.